The present invention relates to a semiconductor device for generating voltages that are used as internal power supply voltages for semiconductor devices, such as, DRAMS, by using an external power supply voltage fed by a peripheral circuitry.
Semiconductor devices, such as, DRAMS, operating at several levels of power supply voltages in the internal circuitry are provided with an up- or a down-converter for up-converting or down-converting an external power supply voltage fed by a peripheral circuitry.
Shown in FIG. 12 is a circuit diagram of a typical up-converter.
The up-converter is provided with an operational amplifier 1, a resistor-voltage divider 5 connected to the positive input terminal of the operational amplifier 1, and an inverter IV1 connected to the output terminal of the operational amplifier 1, a ring oscillator 2 driven by the output of the inverter IV1, a charge pump 3 driven by the output of the ring oscillator 2, and a capacitor Cpp connected to the output terminal of the charge pump 3.
The resistor-voltage divider 5 divides an up-converted voltage Vpp that has been up-converted by the charge pump 3.
The operational amplifier 1 compares a divided voltage TAP of the resistor-voltage divider 5 with a reference voltage VBGR, to output a positive signal if the former voltage level is higher than the latter, whereas a negative signal if the latter is higher than the former.
This results in an output OSCE of the inverter IV1 being brought into a low level state if TAP&gt;VBGR, whereas a high level if TAP&lt;VBGR.
The reference voltage VBGR is set at, for example, 1. 25V, that is generated by a band-gap reference circuit (not shown) exhibiting no thermal behavior.
Illustrated in FIG. 13 are voltage waveforms of the up-converted voltage Vpp, the divided voltage TAP, and the output OSCE of the inverter IV1.
The operation of the up-converter shown in FIG. 12 will be explained with reference to the voltage waveforms illustrated in FIG. 13.
Transition of the up-converted voltage Vpp from its stable condition (a desired voltage level) to a lower level with the divided voltage TAP lower than the reference voltage VBGR triggers the transition of the inverter output voltage OSCE from a low to a high level.
This voltage transition initiates the ring oscillator 2 for oscillation and also the charge pump 3 for up-conversion.
The up-converted voltage Vpp at a high level gradually raises the divided voltage TAP higher than the reference voltage VBGR, thus the inverter output voltage OSCE being brought into a low level state.
This voltage transition halts the oscillation of the ring oscillator 2 and also the up-conversion of the charge pump 3.
Repetition of the operation described above obtains the up-converted voltage Vpp expressed as follows: EQU Vpp={1+(R2/R1)}X VBGR . . . (1)
Shown in FIG. 14 is the equivalent circuit of the operational amplifier 1 of FIG. 12.
The operational amplifier 1 shown in FIG. 14 is provided with PMOS transistors Q1 and Q2 that constitute a current mirror, NMOS transistors Q3 and Q4 that turns on or off according to the logic of an input signal, an NMOS transistor Q5 that enables or disables the operational amplifier 1, and an NMOS transistor Q6 that validates or invalidates the output of the operational amplifier 1.
In FIG. 14, the transistor Q3 turns on when its gate voltage is higher than a gate voltage of the transistor Q4, thus the transistors Q1 and Q2 turn on to generate an output voltage VOUT almost equal to the positive power supply voltage Vdd.
On the other hand, the transistor Q4 turns on when its gate voltage is lower than a gate voltage of the transistor Q3, thus an output voltage VOUT becoming almost equal to the ground level.
Present DRAMs and FRAMs, etc., turn on its up-converter in operation when the memories are on (an operating mode), whereas turns it off when the memories are off (a waiting mode) for power saving. Up-converted power supply voltages are, however, used at many sections of the memories, thus resulting in a heavy load. Such an up-converter control takes a considerably long time for up-converting power supply voltages at desired levels.
An up-converter shown in FIG. 15 has been proposed for solving such a problem.
The up-converter shown in FIG. 15 is provided with a voltage controller 21a for the operating mode and a voltage controller 21b for the waiting mode. Both controllers have almost the same circuitry. An operational amplifier Is of the voltage controller 21b is a low power consumption-type. Resistors R1H and R2H in the voltage controller 21b have resistance higher than those of resistors R1L and R2L in the voltage controller 21a.
The operational amplifier 1a operates when a signal "active" indicating the operating mode is high, whereas and the operational amplifier 1b operates when a signal "standby" indicating the waiting mode is high.
The up-converter shown in FIG. 15, however, has the following drawbacks:
The driving performance of the up-converter is preferably restricted in the waiting mode because almost no circuitry in the semiconductor device operates in this mode. The waiting mode requires a small current consumed by the operational amplifier 1s, while larger resistance for the resistors R1H and R2H that constitute the resistor-voltage divider 5 (FIG. 12) for a small pass-current.
Decrease in current consumed by the operational amplifier 1s can be achieved by a well known technique, such as, provision of a current-limiting transistor.
However, the larger the resistance of the resistors R1H and R2H, the larger the area of resistor-wiring, and the larger the stray capacitance of the resistor-wiring. This results in signal delay due to resistor and capacitor, which causes a low voltage-feedback control.
Not only the up-converter, but also the down-converter has the same disadvantages as discussed below.
Shown in FIG. 16 is a circuit diagram of a typical down-converter.
The down-converter is provided with an operational amplifier 1, a PMOS transistor Q8, and resistors R1 and R2 that constitute a resistor-voltage divider.
Decrease in down-converted voltage Vout lower than a desired voltage causes decrease in a divided voltage TAP of the resistor-voltage divider lower than a reference voltage VBGR, which brings the output of the operational amplifier 1 into a lower level, to turn on the transistor Q8 for raising the voltage Vout.
Shown in FIG. 17 is a circuit diagram of another typical down-converter, provided with voltage controllers for the operating and waiting modes.
Like the up-converter shown in FIG. 12, the down-converter (FIG. 17) inevitably has a large chip size, a large delay through wiring, and a high production cost for power saving in the waiting mode due to the existence of resistor-voltage divider.